1. Field of the Invention
This invention relates to noninverting Bi-CMOS logic gates, and particularly to Bi-CMOS logic gates such as buffers and AND gates, the propagation delays of which are roughly equal to the propagation delay through a single Bi-CMOS inverter.
2. Related Art
A multitude of digital design applications involve placing a noninverting buffer element in a signal path. Conventional noninverting buffer elements in Bi-CMOS technology, however, actually comprise two Bi-CMOS inverters connected in series. The output of a first Bi-CMOS inverter is linked to the input of the second Bi-CMOS inverter. The output of this second Bi-CMOS inverter is the output of the buffer. Such conventional Bi-CMOS buffers, therefore, introduce roughly twice the propagation delay into the signal path than a single Bi-CMOS inverter does.
This large propagation delay of Bi-CMOS buffers is highly undesirable in many applications. In a Bi-CMOS static RAM, for example, the access time between the time when the address appears at the address input pins and the time when the static RAM actually outputs the data is critical. Great expense is directed to reducing this propagation delay.
Inside a static RAM, an address decoder decodes the address onto a series of decoder output lines. Each of the output lines is associated with a memory block. Accordingly, when an address is decoded, one of the output lines is activated. Activation of this output line indicates the memory block to which the address is mapped. Due to the architecture of the decoder, however, both the active high and active low versions of each address input line is required as an input into the decoder.
FIG. 1 (PRIOR ART) shows address input line signal A passing through inverter INV1 so that inverted signal A* is produced. This output is delayed with respect to the address input line signal A by the inverter propagation delay of INV1. Noninverting buffer BUF1 is provided to produce signal A(delayed). Because buffer BUF1 really comprises two inverters, signal A(delayed) is delayed with respect to the address input line signal A by two inverter delays. Therefore, the A(delayed) signal is delayed with respect to the signal A* by one inverter delay. If no buffer were provided, one inverter delay would still exist between signal A* and signal A.
Due to the multiple problems confronting digital designers including the above described time skew problem, it would be desirable to have a Bi-CMOS buffer circuit as well as other noninverting logic gates which have the same delay as a single Bi-CMOS inverter. The speed of the slowest path through the decoder could be increased. Furthermore, because the skew between signals A* and A(delayed) would be reduced, the inputs to the decoder could be readily altered in the event that the decoding logic should be changed.
FIG. 2 (PRIOR ART) is a circuit diagram of a conventional Bi-CMOS inverter. When the voltage on the input 1 to the inverter transitions from a high digital logic voltage to a low digital logic voltage, P channel transistor Q1 turns on and N channel transistor Q2 turns off. As a result, node N1 is driven high, the voltage on the base of bipolar output transistor Q3 increases, and bipolar transistor Q3 turns on. When the voltage on input 1 transition from high to low, N channel transistor Q4 is also turned off. As a result node N2 is pulled low through resistance R1 thereby turning bipolar output transistor Q5 off. With bipolar output transistor Q3 being on and bipolar output transistor Q5 being off, the output 2 of the Bi-CMOS inverter transitions from low to high.
In the case of input 1 transitioning high, node N1 goes low to turn bipolar transistor Q3 off. Transistor Q4 is also turned on. Charge stored in the base of transistor Q5 will pass through transistor Q4, to the collector of now saturated transistor Q5, through transistor Q5 and to ground The voltage on the base of bipolar transistor Q5 therefore increases and bipolar transistor Q5 is turned on. Because bipolar transistor Q5 is on and bipolar transistor Q3 is off, the voltage on the output 2 of the conventional Bi-CMOS inverter transitions from high to low.